1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to a memory device which has dynamic random access memory cells and is compatible with a static random access memory, and a method of driving the same.
2. Description of the Related Art
Generally, random access memory (RAM) is classified into static random access memory (SRAM) and dynamic random access memory (DRAM). RAM typically includes a memory array composed of a plurality of unit memory cells arranged in a matrix form defined by rows and columns, and peripheral circuits adapted to control the input/output of data to/from the unit memory cells. Each of the unit memory cells, which are used in an SRAM to store one bit of data, is implemented with four transistors that form a latch structure, and two transistors that act as transmission gates. In SRAM, since data is stored in unit memory cells each having the latch structure, a refresh operation is not required to maintain the stored data. Further, SRAM has the advantages of a faster operating speed and lower power consumption compared to DRAM.
However, since the unit memory cells of SRAM is each composed of six transistors, SRAM is disadvantageous in that it requires a large wafer area compared to DRAM, in which each unit memory cell is implemented with a transistor and a capacitor. In more detail, in order to manufacture a semiconductor memory device of the same capacity, SRAM requires a wafer area about six to ten times that of DRAM. Such necessity of a large wafer area increases the unit cost of SRAM. When DRAM instead of SRAM is used to reduce costs, however, a DRAM controller is additionally required to perform a periodic refresh operation. Accordingly, the entire performance of a system using DRAM is deteriorated due to the time required to perform the refresh operation and a slower operating speed.
In order to overcome the disadvantages of DRAM and SRAM, there have been developments in SRAM-compatible memory which is externally compatible with SRAM while internally exploiting DRAM cells. FIG. 1 is a graphical view for explaining a method of driving a conventional SRAM-compatible memory. Referring to FIG. 1, a single ‘external access period (EXT-TRC)’ includes an internal access period’ and a ‘refresh period (REF-RW)’.
However, in the conventional SRAM-compatible memory driving method, operations of fetching data stored in a refreshed DRAM cell, transmitting the cell data to a sense amplifier, amplifying the cell data, and then rewriting the cell data in a refreshed DRAM cell are performed within a single ‘refresh period (REF-RW)’.
Therefore, the conventional SRAM-compatible memory and its driving method have problems such that the refresh period REF-RW requires relatively large amount of time, so that the entire operating time is decreased.